1. Field of the Invention
This invention is related to the field of processors and, more particularly, to address translation mechanisms within processors.
2. Description of the Related Art
Processors typically support virtual address translation. Generally, address translation is a process in which a virtual address (generated from one or more address operands of an instruction) is translated to a physical address which identifies a memory location in a memory to which the processor is coupled. Address translation allows for numerous benefits.
For example, by providing address translation, a virtual address space exceeding the actual physical memory space of the computer system may be supported. The application programmer (to which the virtual address space is visible and the physical address space is typically invisible) may be insulated from the different amounts of memory that may be supplied in different computer systems. The operating system on the computer system may allocate physical memory to various virtual addresses, and may store instructions and data for other virtual addresses on a slower backup storage (e.g. disk storage). Generally, a block of contiguous virtual addresses is mapped to a corresponding block of physical addresses by a translation table entry in a translation table maintained by the operating system. The block of contiguous addresses is referred to as a page.
As another example, the translation table entry may include protection information for the page. As the processor translates addresses of memory requests, the processor may verify that the type of request being executed is permitted according to the protection information. If the request is not permitted, the processor may generate an exception instead of completing the request. Thus, the operating system may control the manner in which each process accesses each page.
An additional advantage of virtual addressing may be enjoyed by multitasking operating systems. Various processes which may be concurrently executing within the computer system may produce the same virtual addresses. However, the virtual addresses of one process may be allocated to different physical pages than the same virtual addresses of another process. Thus, the instructions and data belonging to one process may be protected from access and update by another process.
Typically, the operating system maintains one or more translation tables in memory. The translation tables are a predefined data structure including a plurality of translation table entries, each translation table entry storing a translation which maps a page of virtual addresses to a corresponding page of physical addresses. The processor searches the translation tables for a translation for each virtual address generated by the processor. Depending upon the definition of the translation table structure, several memory accesses may be performed prior to finding the correct translation table entry in the translation table.
In order to speed the translation process, most processors implement translation lookaside buffers (TLBs). The TLBs are implemented within the processor and cache translation information from previously used translation table entries. Prior to searching the translation tables in memory for a translation of a virtual address, the processor searches the TLBs. Typically, a portion of the virtual address is compared to virtual address tags stored in the TLB. If a hit in the TLB is detected (i.e. a virtual tag match is detected), the corresponding physical address stored in the TLB is used.
Unfortunately, since the same virtual address may have different translations for different processes, the TLBs typically must be flushed during each process switch (or context switch). If the process which is switched out is switched back in a short time later, the translations corresponding to that process must still be reloaded from memory into the TLB (even though they might not have been deleted if it weren""t for the flushing during the context switch). Processor performance may be lost due to the time required to reload the TLB with the translations corresponding to the process. A method for reducing the number of TLB invalidations due to context switches is therefore desired.
The problems outlined above are in large part solved by a processor as described herein. The processor provides a register for storing an address space number (ASN). Operating system software may assign different ASNs to different processes, and thus the ASN may identify a process. The processor may include a TLB to cache translations, and the TLB may record the ASN from the ASN register in a TLB entry being loaded. Thus, translations may be associated with processes through the ASNs. Generally, a TLB hit will be detected in an entry if the virtual address to be translated matches the virtual address tag and the ASN matches the ASN stored in the register. Accordingly, the TLB need not be invalidated on context switches.
Additionally, the processor may use an indication from the translation table entries to indicate whether or not a translation is global. If a translation is global, then the ASN comparison is not included in detecting a hit in the TLB (and thus determining if the cache translation may be used to translate the virtual address). In other words, the ASN comparison does not affect the detection of a hit on a global translation. Thus, translations which are used by more than one process may not occupy multiple TLB entries. Instead, a hit may be detected on the TLB entry storing the global translation even though the recorded ASN may not match the current ASN. TLB entry usage may thus be more efficient.
In one embodiment, ASNs may be enabled through an enable indication. If ASNs are disabled, the TLB may be flushed on context switches. However, the indication from the translation table entries used to indicate that the translation is global may be used (when ASNs are disabled) by the TLB to selectively invalidate non-global translations on a context switch while not invalidating global translations on the context switch.
Broadly speaking, a processor is contemplated. The processor comprises a first register and a TLB coupled to the first register. The first register is configured to store a first value indicative of a first process being executed by the processor. The TLB includes at least a first entry, wherein the first entry is configured to store at least: (i) a portion of a first virtual address; (ii) a second value indicative of a second process being executed by the processor at a time that the first entry is loaded with the first virtual address; and (iii) a first indication from a translation table entry corresponding to the first virtual address. The TLB is configured to selectively include, dependent upon the first indication, a comparison of the first value to the second value in determining if a second virtual address hits in the first entry.
Additionally, a method is contemplated. A first virtual address is presented to a TLB for translation. The TLB determines if the first virtual address is a hit in a first entry of the TLB. The first entry stores at least: (i) a portion of a second virtual address; (ii) a first value indicative of a first process being executed at a time that the first entry is loaded with the second virtual address; and (iii) a first indication from a translation table entry corresponding to the second virtual address. The determination selectively includes comparing said first value to a second value indicative of a second process being executed during the determination. The selective including is dependent upon the first indication.